A Novel Simulation and Veri cation Approach in an ASIC Design Process
نویسندگان
چکیده
|We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and veri cation. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation of implemented algorithms. We present here our design environment and experience that we gained from the design process. Keywords|ASIC design ow, combined simulations, complex design environment, test-vector generation.
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